Technical Field
The present invention generally relates to semiconductor device fabrication and, more particularly, to the formation of transistors having nanosheet channels.
Description of the Related Art
Field effect transistors (FETs) are semiconductor devices that use an electric field generated by a gate structure to influence the behavior of charge carriers within a semiconductor channel structure. The geometry of the channel structure can significantly impact the electrical properties of the device. N-type field effect transistors (NFET) and p-type field effect transistors (PFET) are two types of complementary metal oxide semiconductor FETs (MOSFETs). The NFET uses electrons as the current carriers and with n-doped source and drain junctions. The PFET uses holes as the current carriers and with p-doped source and drain junctions.
Nanosheet channel structures present one option for scaling device architectures to smaller sizes. Nanosheet (or nanowire) FET devices are considered to be a viable option for continued CMOS to the 7 nm node and beyond. However, current nanosheet fabrication processes use epitaxial processes that result in relatively low-quality nanosheet structures, resulting in poor device performance. In addition, in conventional nanosheet CMOS integration processes, silicon germanium sacrificial layers are removed and silicon layers are used as channels in nFET device regions, while silicon sacrificial layers are removed and silicon germanium layers are used as channels in pFET device regions. This will introduce topography issues in the downstream device fabrication processes since the channels in the respective regions would be offset relative to each other and thus would not be at the same level in the final device.